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| rev. 1.2 feburary 2009 ddr sdram k4h281638l 1 of 32 128mb l-die ddr sdram specification 66 tsop-ii (rohs compliant) with lead-free and halogen-free * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or other- wise, to any intellectual property rights in samsung products or technol- ogy. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sa msung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or
rev. 1.2 feburary 2009 ddr sdram k4h281638l 2 of 32 1.0 key features ............ ................. ................ ................ ................. ................ ............... ........... .......4 2.0 ordering information .... ................ ................. ................ ................ ................. ............... .............4 3.0 operating frequencies ............. ................ ................ .............. ............... .............. ............ ...........4 4.0 pin / ball description ................ .............. .............. .............. .............. .............. ............. ...............5 5.0 package physical dimension ...... ................. ................ .............. .............. .............. .............. .....7 6.0 block diagram (2mb x 16 i/o x4 banks) .................. ................. ................ ................. ................ 9 7.0 functional description .................. .............. .............. .............. .............. .............. ............10 7.1 power-up & initialization sequence ............. ................ ................. ................ ................. ..............10 7.2 mode register definition ................ ................. ................ ................ ................. .............. ............11 7.3 extended mode register set(emrs) ................. ................ ................ ................. .............. ............13 8.0 input/output function description .. ................ .............. .............. ............... .............. ............. .14 9.0 command truth table .... ................. ................ ................ ................. ................ ................ ........15 10.0 general description .... ................ ................. ................ ................ ................. ............... ...........16 11.0 absolute maximum rating ......... ................. ................ .............. .............. .............. ............. ....16 12.0 dc operating conditions ................ ................ ................. ................ ................. ............... ......16 13.0 ddr sdram spec it ems & test conditions ........ ................. ................ ................. ..............17 14.0 input/output capacitance ............... ................ ................. ................ ................. ............... ......17 15.0 detailed test condition for d dr sdram idd1 & idd7a .. .............. .............. .............. ..........18 16.0 ddr sdram idd spec table ......... ................ ................ .............. ............... .............. ............ ..19 17.0 ac operating conditions ................ ................ ................. ................ ................. ............... ......20 18.0 ac overshoot/undershoot speci fication for address and control pi ns ............. ..............20 19.0 overshoot/undershoot specification for data, strobe and m ask pins ........... ............ .......21 20.0 ac timming parameters & specifications ........... ................. ................ ................. ..............22 21.0 system character istics for ddr sdram ........... .............. .............. .............. .............. ..........23 22.0 component notes ....... ................ ................. ................ ................ ................. ................ ..........24 23.0 system notes ......... ................. ................ ................ ................. ................ ................. ..............26 24.0 ibis : i/v characteris tics for input and output bu ffers ............... .............. .............. ............27 table of contents rev. 1.2 feburary 2009 ddr sdram k4h281638l 3 of 32 revision history revision month year history 1.0 september 2008 - release rev.1.0 spec - corrected max tck complying jedec 1.1 october 2008 - changed tck max of 400/333mbps to 10ns from 12ns - corrected idd1 current measurement condition 1.2 february 2009 - added fbga package spec - corrected matched drive strength spec. rev. 1.2 feburary 2009 ddr sdram k4h281638l 4 of 32 ? v dd : 2.5v 0.2v, v ddq : 2.5v 0.2v for ddr333, 400 ? v dd : 2.5v 5%, v ddq : 2.5v 5% for ddr500 ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe [l(u)dqs] (x16) ? four banks operation ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? mrs cycle with address key programs -. read latency : ddr333(2.5 clock), ddr400(3 clock), ddr500(3 clock) -. burst length (2, 4, 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the positive go ing edge of the system clock(ck) ? data i/o transactions on both edges of data strobe ? edge aligned data output, center aligned data input ? ldm,udm for write masking only (x16) ? auto & self refresh ? 15.6us refresh interval(4k/64ms refresh) ? maximum burst refresh cycle : 8 ? 66pin tsop ii lead-free and halogen-free package ? rohs compliant cd(ddr500@cl=3) cc(ddr400@cl=3) b3(ddr333@cl=2.5) speed @cl2 n/a n/a n/a speed @cl2.5 166mhz 166mhz 166mhz speed @cl3 250mhz 200mhz - cl-trcd-trp 3-4-4 3-3-3 2.5-3-3 part no. org. max freq. interface package note k4h281638l-lccd 8m x 16 cd(ddr500@cl=3) sstl2 66pin tsop ii lead-free & halogen-free k4h281638l-lccc cc(ddr400@cl=3) K4H281638L-LCB3 b3(ddr333@cl=2.5) 1.0 key features 2.0 ordering information 3.0 operating frequencies rev. 1.2 feburary 2009 ddr sdram k4h281638l 5 of 32 dm is internally loaded to match dq and dqs identically. row & column address configuration organization row address column address 8mx16 a0~a11 a0-a8 4.0 pin / ball description 128mb tsop-ii package pinout 1 66pin tsop ii (400mil x 875mil) 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 27 26 25 24 23 22 21 54 53 52 51 50 49 48 47 46 45 44 43 35 36 37 38 39 40 41 42 55 56 57 58 59 60 34 (0.65mm pin pitch) 33 32 31 30 29 28 61 62 63 64 65 66 bank address ba0~ba1 auto precharge a10 v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq ba 0 cs ras cas we ldm v ddq dq 7 v dd a 3 a 2 a 1 a 0 ap/a 10 ba 1 nc ldqs nc nc nc v dd v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq a 11 cke ck udm v ref v ssq dq 8 v ss a 4 a 5 a 6 a 7 a 8 a 9 nc udqs nc v ss ck nc nc 8mb x 16 66pin tsop - ii rev. 1.2 feburary 2009 ddr sdram k4h281638l 6 of 32 60ball fbga (top view) dm is internally loaded to match dq and dqs identically. row & column address configuration organization row address column address 4mx16 a0~a11 a0-a7 9 v ddq dq1 dq3 dq5 dq7 nc 8 dq0 v ssq v ddq v ssq v ddq v dd cas cs ba0 a10/ap a1 a3 7 v dd dq2 dq4 dq6 ldqs ldm we ras ba1 a0 a2 v dd a b c d e f g h j k l m 3 v ss dq13 dq11 dq9 udqs udm ck cke a9 a7 a5 v ss 2 dq15 v ddq v ssq v ddq v ssq v ss ck nc a11 a8 a6 a4 1 v ssq dq14 dq12 dq10 dq8 v ref 4m x 16 64mb fbga package ballout rev. 1.2 feburary 2009 ddr sdram k4h281638l 7 of 32 5.0 package physical dimension 66pin tsop(ii) package dimension #1 (1.50) (1.50) #66 #34 #33 10.16 0.10 ( r 0 . 1 5 ) 22.22 0.10 0.210 0.05 0.665 0.05 ( r 0 . 1 5 ) (0.71) [0.65 0.08] 0.65typ 0.30 (10 ) (10 ) (10.76) 0.125 +0.075 - 0.035 (10 ) (10 ) 11.76 0.20 (0.80) (0.80) (0.50) (0.50) (4 ) 0.45 ~ 0.75 (0 8 ) 0.25typ ( r 0 . 2 5 ) ( r 0 . 2 5 ) 0.08 1.00 0.10 0.05 min 1.20 max 0.10 max 0.075 max [ [ note 1. ( ) is reference 2. [ ] is ass?y out quality detail a detail b detail b detail a 0.25 0.08 unit : mm rev. 1.2 feburary 2009 ddr sdram k4h281638l 8 of 32 60ball fbga 64mb package dimension 8.0 0 0.10 12.00 0.10 0.10 max 0.32 0.05 1.10 0.10 8.00 0.10 a b c d e f g h j k l m 0.80 0.50 1.00 x 11 = 11.00 12.00 0.10 60 - ? 0.45 solder ball top view bottom view 1.00 #a1 1.60 #a1 mark ? 0.20 m ab (datum a) (datum b) 0.80 x 8 = 6.40 a b 1 2 3 4 5 6 7 8 9 (post reflow 0.50 0.05) units : millimeters rev. 1.2 feburary 2009 ddr sdram k4h281638l 9 of 32 6.0 block diagram (2mb x 16 i/o x4 banks) bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 1mx32 1mx32 1mx32 1mx32 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register dll strobe gen. ck, ck add lcke ck, ck cke cs ras cas we ck, ck lcas lras lcbr lwe lwcbr lras lcbr ck, ck x8/16/32 32 16 x4/8/16 lwe 16 dqi data strobe ludm (x16) ludm (x16) dm input register ludm (x16) rev. 1.2 feburary 2009 ddr sdram k4h281638l 10 of 32 ddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. no power sequencing is spec ified during power up and power down given the following ?v dd and v ddq are driven from a single power converter output, and ?v tt is limited to 1.35 v, and ?v ref tracks v ddq /2 or, the following relati onships must be followed: ?v ddq is driven after or with v dd such that ?v ddq < v dd + 0.3 v and ?v tt is driven after or with v ddq such that v tt < v ddq + 0.3 v, and ?v ref is driven after or with v ddq such that v ref < v ddq + 0.3 v. at least one of these two conditions must be met. except for cke, inputs are not recognized as valid until after v ref is applied. cke is an sstl_2 input, but will detect an lvcmos low level after v dd is applied. maintaining an lvcmos low level on cke duri ng power up is required to guarantee that the dq and dqs outputs will be in the high?z state, where they will remain un til driven in normal operation (by a read access). after all powe r supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable c om- mand. once the 200 s delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command sh ould be applied. next a mode register set command should be issued for the extended mode register, to enable the dll, then a mode register set command should be issued for the mode register, to reset the dll, and to program the operati ng parameters. 200 clock cycles are required between the dll reset a nd any read command. a precharge all command should be applied, placing the device in the ?all banks idle? state. once in the idle state, two au to refresh cycles must be performed. additionally, a mode register set co mmand for the mode reg- ister, with the reset dll bit deactivated (i.e., to program ope rating parameters without resetting the dll) must be performed. following these cycles, the ddr sdram is ready for normal operation. 7.1 power-up & init ialization sequence 7.0 functional description rev. 1.2 feburary 2009 ddr sdram k4h281638l 11 of 32 the mode register stores the data for controlling the vari ous operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset and various vendor specif ic options to make ddr sdram useful for variety of different appli- cations. the default value of the mode r egister is not defined, theref ore the mode register must be written after emrs settin g for proper ddr sdram operation. the mode register is written by asserting low on cs , ras , cas , we and ba0(the ddr sdram should be in all bank precharge with cke already high prior to writing into t he mode register). the states of address pins a0 ~ a11 in the same cycle as cs , ras , cas , we and ba0 going low are written in the mo de register. two clock cycles are requested to complete the write opera- tion in the mode register. the mode register contents can be changed using the same command and clock cycle requirements durin g operation as long as all banks are in the idle state. the mode register is divided into various fields depending on functionali ty. the burst length uses a0 ~ a2, addressing mode uses a3, cas latency(read latency from column address) uses a4 ~ a6. a7 is used for test mode. a8 is used for dll reset. a7 must be set to low for normal mrs operation. refer to the table for specific codes for var ious burst lengths, addressing modes and cas latencies. ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 rfu 0 rfu dll tm cas latency bt burst length cas latency a 6 a 5 a 4 latency 0 0 0 reserve 0 0 1 reserve 0 1 0 reserve 011 3 1 0 0 reserve 1 0 1 reserve 110 2.5 1 1 1 reserve burst length a 2 a 1 a 0 burst length sequential interleave 0 0 0 reserve reserve 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve a 7 mode 0normal 1test a 3 burst type 0 sequential 1 interleave * rfu(reserved for future use) must stay "0" during mrs cycle. a 8 dll reset 0no 1yes ba0 an ~ a0 0 (existing)mrs cycle 1 extended funtions(emrs) address bus mode register note : *1 a12 is used for 256mb only. that is 128mb uses a0~a11 mode regist er set(mrs) 7.2 mode register definition rev. 1.2 feburary 2009 ddr sdram k4h281638l 12 of 32 mode register set *1 : mrs can be issued only at all bank precharge state. *2 : minimum trp is required to issue mrs command. command 2 01 5 34 8 67 t ck 2 clock min. precharge all banks mode register set t rp *2 *1 any command ck ck burst address ordering for burst length burst length starting address(a2, a1, a0) sequential mode interleave mode 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 rev. 1.2 feburary 2009 ddr sdram k4h281638l 13 of 32 the extended mode register stores the data for enabling or disabling dll, and selecti ng output driver size. the default value of the extended mode register is not defined, theref ore the extened mode register must be written after power up for enabling or disab ling dll. the extended mode register is wr itten by asserting low on cs , ras , cas , we and high on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writ ing into the extended mode register). the state of address pins a0 ~ a11 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. "high" on ba0 is used for emrs. all the other add ress pins except a0, a1, a6, a11 and ba0 must be set to low for proper emrs operation. refer to the table for specific codes. figure 7. extend mode register set address bus extended a 0 dll enable 0 enable 1 disable ba 0 a n ~ a 0 0mrs 1emrs a6 a1 output driver impedence contol 00 full 0 1 weak 11 matced dll enable/disable the dll must be enabled for normal operation. dll enable is required during powerup initialization, and upon returning to norma l operation after having disabled the dll for the purpose of debug or evaluation (upon exiting self refresh mode, the dll is enab led automatically). any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. samsung supports a weak driver strength option, intended for lighter load and/or point-to-point environments. i-v curves for the normal drive strength and weak drive strength are inclu ded in 11.1~2 of this document. *rfu : should stay " 0" during emrs cycle. ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 *rfu 1 d.i.c *rfu d.i.c *rfu d.i.c dll mode register a11 vendor id & die status identi- fication 0off 1on manufacturers vendor code and die status identification the manufacturers vendor code, v, is selected by issuing a extended mode register set command with bits a11 set to one, and bits a0-a10 set to the desired values. when the v function is enabled the 128mb ddr sdram will provide its manufacturers ve ndor code and die status identification on dq[1:0]. dq[1:0] vendor id/dsi 00 samsung / pass 01 samsung / fail 10 reserved / pass 11 reserved / fail 7.3 extended mode register set(emrs) rev. 1.2 feburary 2009 ddr sdram k4h281638l 14 of 32 symbol type description ck, ck input clock : ck and ck are differential clock inputs. all address and control input signals are sam- pled on the positive edge of ck and negative edge of ck . output (read) data is referenced to both edges of ck. internal clock signals are derived from ck/ck . cke input clock enable : cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power- down and self refresh operation (all banks idle), or active power down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit, and for output disable. cke must be maintained high throughput read and write accesses. input buffers, excluding ck, ck and cke are disabled during power down. in put buffers, excluding cke are disabled during self refresh. cke is an sstl_2 input, but will detect an lvcmos low level after v dd is applied upon 1st power up, after v ref has become stable during the power on and ini- tialization sequence, it must be maintained for proper operation of the cke receiver. for proper self refresh entry and exit, v ref must be maintained to this input. cs input chip select : cs enables(registered low) and disables(registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on system s with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs : ras , cas and we (along with cs ) define the command being entered. ldm,(udm) input input data mask : dm is an input mask signal fo r write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. for the x16, ldm corresponds to the data on dq0~d7 ; udm corresponds to the data on dq8~dq15. dm may be driven high, low, or floating during reads. ba0, ba1 input bank addres inputs : ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a [0 : 11] input address inputs : provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the mem- ory array in the respective bank. a10 is sampled during a precharge command to deter- mine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op code during a mode regi ster set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). dq i/o data input/output : data bus ldqs,(u)dqs i/o data strobe : output with read data, input with write data. edge-align ed with read data, cen- tered in write data. used to capture write data . for the x16, ldqs corresponds to the data on dq0~d7 ; udqs corresponds to the data on dq8~dq15. nc - no connect : no internal electrical connection is present. v ddq supply dq power supply : +2.5v 0.2v. v ssq supply dq ground. v dd supply power supply : +2.5v 0.2v. v ss supply ground. v ref input sstl_2 reference voltage. 8.0 input/output function description rev. 1.2 feburary 2009 ddr sdram k4h281638l 15 of 32 (v=valid, x=don t care, h=logic high, l=logic low) note : 1. op code : operand code. a 0 ~ a 11 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/mrs can be issued onl y at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row acti ve and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. udm/ldm(x16 only) sampled at the rising and falling edges of the udqs/ldqs and data-in are masked at the both edges (write udm/ldm latency is 0). 9. this combination is not defined for any function, which means "no operation(nop)" in ddr sdram. command cken-1 cken cs ras cas we ba0,1 a10/ap a0 ~ a9, a11 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll l h x 3 self refresh entry l 3 exit l h lh h h x 3 hx x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable hxlhlhv l column address 4 auto precharge enable h 4 write & column address auto precharge disable hxlhllv l column address 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lv v v exit l h x x x x precharge power down mode entry h l hx x x x lh h h exit l h hx x x lv v v udm/ldm for x16 h x x 8 no operation (nop) : not defined h x hx x x x 9 lh h h 9 9.0 command truth table rev. 1.2 feburary 2009 ddr sdram k4h281638l 16 of 32 2m x 16bit x 4 banks doub le data rate sdram the k4h281638l is 134,217,728 bits of double data rate synchronous dram organized as 4x 2,097,152 words by 16bits, fabricated with samsung s high performance cmos technology. sync hronous features with data strobe a llow extremely high performance up to 500mb/s per pin. i/o transactions are possible on both edges of dqs. range of operating frequencie s, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restri cted to recommend operation condition. exposure to higher than recommended voltage for extended per iods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd & v ddq supply relative to v ss v dd , v ddq 1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1w short circuit current i os 50 ma 10.0 general description 11.0 absolute maximum rating recommended operating conditions(voltage referenced to v ss =0v, ta=0 to 70 c ) note : 1. v ref is expected to be equal to 0.5*v ddq of the transmitting device, and to track variations in the dc level of same. peak-to peak noise on v ref may not exceed +/-2% of the dc value. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track vari- ations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the ratio of the pullup current to the pulldown current is s pecified for the same temperature and voltage, over the entire t emperature and voltage range, for device drain to source voltages from 0.25v to 1.0v. for a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. the full variation in the ratio of t he maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0. parameter symbol min max unit note supply voltage (for device with a nominal v dd of 2.5v for ddr333, 400) v dd 2.3 2.7 v supply voltage (for device with a nominal v dd of 2.5v for ddr500) v dd 2.375 2.625 v i/o supply voltage (for device with a nominal v dd of 2.5v for ddr333, 400) v ddq 2.3 2.7 v i/o supply voltage (for device with a nominal v dd of 2.5v for ddr500) v ddq 2.375 2.625 v i/o reference voltage v ref 0.49*v ddq 0.51*v ddq v1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.36 v ddq +0.6 v3 v-i matching: pullup to pulldown current ratio v i (ratio) 0.71 1.4 - 4 input leakage current i i -2 2 ua output leakage current i oz -5 5ua output high current(full strengh driver) ; v out =v ddq -0.388v i oh -13.8 -16.1 ma output lowcurrent(full strengh driver) ; v out =0.388v i ol 16.5 19.2 ma output high current(week strengh driver) ; v out =v ddq -0.538v i oh -18.2 -21.8 ma output low current(week strengh driver) ; v out =0.538v i ol 20.2 24.5 ma output high current(mached strengh driver) ; v out =v ddq -0.6505v i oh -15.5 -18.9 ma output low current(mached strengh driver) ; v out =0.6505v i ol 17 21.3 ma 12.0 dc operating conditions rev. 1.2 feburary 2009 ddr sdram k4h281638l 17 of 32 conditions symbol operating current - one bank active-precharge; trc=trcmin; tck= 6ns for ddr333, 5ns for ddr400, 4ns for ddr500; dq,dm and dqs inputs cha nging once per clock cycle; address and control i nputs changing once every two clock cycles. idd0 operating current - one bank operation ; one bank open, bl=4, reads - refer to the following page for detailed test condition idd1 precharge power-down standby current; all banks idle; power - down mode; cke = rev. 1.2 feburary 2009 ddr sdram k4h281638l 18 of 32 idd7a : operating current: four bank operation 1. typical case: v dd = 2.5v, t=25 c worst case : v dd = 2.7v, t= 10 c 2. four banks are being interleaved with trc(min), bu rst mode, address and control inputs on nop edge are not changing. lout = 0ma 4. timing patterns - b3(166mhz,cl=2.5) : tck=6ns, bl =4, trrd=2*tck, trcd=3*tck, tras=5*tck read : a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 - repeat the same timing with random address changing *50% of data changing at every burst - cc(200mhz,cl = 3) : tck = 5ns, bl = 4, trrd=2*tck, trcd = 3*tck , tras = 8*tck read : a0 n a1 ra0 a2 ra1 a3 ra2 n ra 3 - repeat the same timing with random address changing *50% of data changing at every transfer - cd(250mhz,cl = 3) : tck = 4ns, cl = 3, bl = 4, trcd = 4*tck , tras = 10*tck read : a0 n n a1 ra0 a2 ra1 a3 ra2 n ra3 - repeat the same timing with random address changing *50% of data changing at every transfer legend : a=activate, r=read, w=write, p=precharge, n=deselect idd1 : operating current: one bank operation 1. typical case: v dd = 2.5v, t=25 c worst case : v dd = 2.7v, t= 10 c 2. only one bank is accessed with t rc(min), burst mode, address and contro l inputs on nop edge are changing once per clock cycle. lout = 0ma 3. timing patterns - b3(166mhz, cl=2.5) : tck=6ns, cl=2.5, bl=4, trcd=3*tck, trc = 10*tck, tras=7*tck read : a0 n n r0 n n n p0 n n - repeat the same timing with random address changing *50% of data changing at every burst - cc(200mhz,cl = 3) : tck = 5ns, cl = 3, bl = 4, trcd = 3*tck , trc = 11*tck, tras = 8*tck read : a0 n n r0 n n n n p0 n n - repeat the same timing with random address changing *50% of data changing at every transfer - cd(250mhz,cl = 3) : tck = 4ns, cl = 3, bl = 4, trcd = 4*tck , trc = 13*tck, tras = 10*tck read : a0 n n n r0 n n n n n p0 n n - repeat the same timing with random address changing *50% of data changing at every transfer legend : a=activate, r=read, w=write, p=precharge, n=deselect 15.0 detailed test condition for ddr s dram idd1 & idd7a rev. 1.2 feburary 2009 ddr sdram k4h281638l 19 of 32 (v dd =2.7v, t = 10 c) symbol 8mx16 (k4h281638l) unit cd(ddr500@cl=3) cc(ddr400@cl=3) b3(ddr333@cl=2.5) idd0 120 110 100 ma idd1 130 120 120 ma idd2p 8 ma idd2f 40 40 40 ma idd2q 40 40 40 ma idd3p 40 35 35 ma idd3n 55 55 55 ma idd4r 200 180 160 ma idd4w 200 180 160 ma idd5 200 180 160 ma idd6 normal 3 3 3 ma idd7a 300 300 280 ma 16.0 ddr sdram idd spec table rev. 1.2 feburary 2009 ddr sdram k4h281638l 20 of 32 note : 1. v id is the magnitude of the difference between the input level on ck and the input level on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 3. v ref is expected to equal v ddq /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v ddq /2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref by-pass capacitor. parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih (ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals. v il (ac) v ref - 0.31 v input differential voltage, ck and ck inputs v id (ac) 0.7 v ddq +0.6 v1 input crossing point voltage, ck and ck inputs v ix (ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v2 i/o reference voltage v ref (ac) 0.45 x v ddq 0.55 x v ddq v 3 parameter specification ddr400 ddr333 maximum peak amplitude allowed for overshoot 1.5 v 1.5 v maximum peak amplitude allowed for undershoot 1.5 v 1.5 v the area between the overshoot signal and v dd must be less than or equal to 4.5 v-ns 4.5 v-ns the area between the undershoot signal and gnd mu st be less than or equal to 4.5 v-ns 4.5 v-ns 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 0.5 0.6875 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.3125 6.5 7.0 v dd overshoot maximum amplitude = 1.5v area maximum amplitude = 1.5v undershoot gnd volts (v) tims(ns) ac overshoot/undershoot definition 17.0 ac operating conditions 18.0 ac overshoot/unde rshoot specification for address and control pins rev. 1.2 feburary 2009 ddr sdram k4h281638l 21 of 32 parameter specification ddr400 ddr333 maximum peak amplitude allowed for overshoot 1.2 v 1.2 v maximum peak amplitude allowed for undershoot 1.2 v 1.2 v the area between the overshoot signal and v dd must be less than or equal to 2.4 v-ns 2.4 v-ns the area between the undershoot signal and gn d must be less than or equal to 2.4 v-ns 2.4 v-ns 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0 v ddq overshoot maximum amplitude = 1.2v area maximum amplitude = 1.2v undershoot gnd volts (v) tims(ns) dq/dm/dqs ac overshoot/undershoot definition 19.0 overshoot/undershoot specification for data , strobe and mask pins rev. 1.2 feburary 2009 ddr sdram k4h281638l 22 of 32 parameter symbol cd (ddr500@cl=3.0) cc (ddr400@cl=3.0) b3 (ddr333@cl=2.5) unit note min max min max min max row cycle time trc 52 - 55 - 60 - ns refresh row cycle time trfc 60 - 70 - 72 - ns row active time tras 36 70k 40 70k 42 70k ns ras to cas delay trcd 16 - 15 - 18 - ns row precharge time trp 16 - 15 - 18 - ns row active to row active delay trrd 12 - 10 - 12 - ns write recovery time twr 12 - 15 - 15 - ns last data in to read command twtr 2 - 2 - 1 - tck clock cycle time cl=2.5 tck 6 10 6 10 6 10 ns cl=3.0 4 8 5 8 -- clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ck tdqsck -0.6 +0.6 -0.6 +0.6 -0.6 +0.6 ns output data access time from ck/ck tac -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 ns data strobe edge to ouput data edge tsop tdqsq - 0.4 - 0.4 - 0.45 ns 22 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.85 1.15 0.72 1.28 0.75 1.25 tck dqs-in setup time twpres 0 - 0 - 0 - ns 13 dqs-in hold time twpreh 0.35 - 0.25 - 0.25 - tck dqs falling edge to ck rising-setup time tdss 0.2 - 0.2 - 0.2 - tck dqs falling edge from ck rising-hold time tdsh 0.2 - 0.2 - 0.2 - tck dqs-in high level width tdqsh 0.4 - 0.35 - 0.35 - tck dqs-in low level width tdqsl 0.4 - 0.35 - 0.35 - tck address and control input setup time(fast) tis 0.9 - 0.6 - 0.75 - ns 15, 17~19 address and control input hold time(fast) tih 0.9 - 0.6 - 0.75 - ns 15, 17~19 address and control input setup time(slow) tis 0.9 - 0.7 - 0.8 - ns 16~19 address and control input hold time(slow) tih 0.9 - 0.7 - 0.8 - ns 16~19 data-out high impedence time from ck/ck thz -0.7 +0.7 -0.65 +0.65 -0.7 +0.7 ns 11 data-out low impedence time from ck /ck tlz -0.7 +0.7 -0.65 +0.65 -0.7 +0.7 ns 11 mode register set cycle time tmrd 8 - 10 - 12 - ns dq & dm setup time to dqs tds 0.4 - 0.4 - 0.45 - ns j, k dq & dm hold time to dqs tdh 0.4 - 0.4 - 0.45 - ns j, k control & address input pulse width tipw 2.2 - 2.2 - 2.2 - ns 18 dq & dm input pulse width tdipw 1.75 - 1.75 - 1.75 - ns 18 exit self refresh to non-read command txsnr 75 - 75 - 75 - ns exit self refresh to read command txsrd 200 - 200 - 200 - tck refresh interval time trefi 15.6 15.6 15.6 us 14 output dqs valid window tqh thp -tqhs - thp -tqhs - thp -tqhs - ns 21 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - ns 20, 21 data hold skew factor tsop tqhs 0.4 0.5 0.55 ns 21 dqs write postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 12 active to read with auto precharge command trap 16 - 15 - 18 - autoprecharge write recovery + precharge time tdal (twr/tck) + (trp/tck) - (twr/tck) + (trp/tck) - (twr/tck) + (trp/tck) - tck 23 power down exit tpdex 1-1-1- tck 20.0 ac timming parameters & specifications rev. 1.2 feburary 2009 ddr sdram k4h281638l 23 of 32 the following specification parameters are required in systems using ddr400 and ddr333 devices to ensure proper system perfor- mance. these characteristics are for system si mulation purposes and are guaranteed by design. table 1 : input slew rate fo r dq, dqs, and dm table 2 : input setup & hold time derating for slew rate table 3 : input/output setup & ho ld time derating for slew rate table 4 : input/output setup & hold de rating for rise/fall delta slew rate table 5 : output slew rate char acteristice (x4, x8 devices only) table 6 : output slew rate characteristice (x16 devices only) table 7 : output slew rate ma tching ratio characteristics ac characteristics symbol ddr400 ddr333 units notes parameter min max min max dq/dm/dqs input slew rate measured between v ih (dc), v il (dc) and v il (dc), v ih (dc) dcslew 0.5 4.0 0.5 4.0 v/ns a, l input slew rate ? tis ? tih units notes 0.5 v/ns 0 0 ps i 0.4 v/ns +50 0 ps i 0.3 v/ns +100 0 ps i input slew rate ? tds ? tdh units notes 0.5 v/ns 0 0 ps k 0.4 v/ns +75 +75 ps k 0.3 v/ns +150 +150 ps k delta slew rate ? tds ? tdh units notes +/- 0.0 v/ns 0 0 ps j +/- 0.25 v/ns +50 +50 ps j +/- 0.5 v/ns +100 +100 ps j slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h ac characteristics ddr400 ddr333 notes parameter min max min max output slew rate matching ratio (pullup to pulldown) 0.67 1.5 0.67 1.5 e, l 21.0 system charact eristics for ddr sdram rev. 1.2 feburary 2009 ddr sdram k4h281638l 24 of 32 1. all voltages referenced to v ss . 2. tests for ac timing, idd, and electrical, ac and dc charac teristics, may be conducted at nominal reference/supply voltage l evels, but the related specifications and device operat ion are guaranteed for the full voltage range specified. 3. figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. it is not int ended to be either a precise representation of the typical system en vironment nor a depiction of the actual load presented by a produc tion tester. system designers will use ib is or other simulation tools to correlate the timing reference load to a system envir onment. manufacturers will correlate to their production test c onditions (generally a coaxial transmission line terminated at the tester elec- tronics). 4. ac timing and idd tests may use a v il to v ih swing of up to 1.5 v in the test enviro nment, but input timing is still referenced to v ref (or to the crossi ng point for ck/ck ), and parameter specifications are guaranteed for the specified ac input levels under nor- mal use conditions. the minimum slew rate for the input signals is 1 v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (be low) the dc input low (high) level. 6. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.2v ddq is recognized as low. 7. enables on.chip refresh and address counters. 8. idd specifications ar e tested after the device is properly initialized. 9. the ck/ck input reference level (for timing referenced to ck/ck ) is the point at which ck and ck cross; the input reference level for signals other than ck/ck , is v ref . 10. the output timing reference voltage level is v tt . 11. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not reference d to a specific voltage level but specify when the device output is no long er driving (hz), or begins driving (lz). 12. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter , but sys tem performance (bus turnaround) will degrade accordingly. 13. the specific requirement is t hat dqs be valid (high, low, or at some point on a valid transition) on or before this ck edge . a valid transition is defined as monotonic and meeting th e input slew rate specifications of the device. when no writes we re previ ously in progress on the bus, dqs will be transitioning fr om high- z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 14. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 15. for command/address input slew rate 1.0 v/ns 16. for command/address input slew rate 0.5 v/ns and < 1.0 v/ns output v tt 50 ? 30pf (vout) figure 1 : timing reference load 22.0 component notes rev. 1.2 feburary 2009 ddr sdram k4h281638l 25 of 32 component notes 17. for ck & ck slew rate 1.0 v/ns 18. these parameters guarantee device timing, but they are no t necessarily tested on each device. they may be guaranteed by device design or tester correlation. 19. slew rate is measured between v oh (ac) and v ol (ac). 20. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limi ts for tcl and tch).....for example, tcl and tch are = 50% of th e period, less the half period jitter (tjit(hp)) of the cl ock source, and less the half period jitter due to crosstalk (tji t(crosstalk)) into the clock traces. 21. tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defined by clock hi gh or clock low (tch, tcl). tqhs accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one tansition followed by the worst case pull-in of dq on the next transition, both of wh ich are, separately, due to data pin skew and output pattern effect s, and p- channel to n-channel variation of the output drivers. 22. tdqsq consists of data pin skew and output pattern effects, and p-channel to n-channel variat ion of the output drivers for any given cycle. 23. tdal = (twr/tck) + (trp/tck) for each of the terms above, if not already an integer, round to the next highest integer. example: for ddr400 at cl=3 an d tck=5ns tdal = (15 ns / 5 ns) + (15 ns/ 5 ns) = (3) + (3) tdal = 6 clocks rev. 1.2 feburary 2009 ddr sdram k4h281638l 26 of 32 b. pulldown slew rate is measured under the test conditions shown in figure 3. output test point v ddq 50 ? figure 3 : pulldown slew rate test load c. pullup slew rate is measured between (v ddq /2 - 320 mv +/- 250 mv) pulldown slew rate is measured between (v ddq /2 + 320 mv +/- 250 mv) pullup and pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only on e output switching. example : for typical slew rate, dq0 is switching for minmum slew rate, all dq bits are switching from either high to low, or low to high. the remaining dq bits remain the same as for previous state. d. evaluation conditions typical : 25 c (t ambient), v ddq = 2.5v, typical process minimum : 70 c (t ambient), v ddq = 2.3v, slow - slow process maximum : 0 c (t ambient), v ddq = 2.7v, fast - fast process e. the ratio of pullup slew rate to pulldown slew rate is spec ified for the same temperature and voltage, over the entire tempe rature and voltage range. for a given output, it represents the maxi mum difference between pullup and pulldown drivers due to process variation. f. verified under typical conditions for qualification purposes. g. tsopii package divices only. h. only intended for operation up to 500 mbps per pin. i. a derating factor will be used to increase tis and tih in the case where the input slew rate is below 0.5v/ns as shown in table 2. the input slew rate is bas ed on the lesser of the slew rates detemined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc), similarly for rising transitions. j. a derating factor will be used to increas e tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tabl es 3 & 4. input slew rate is based on the larger of ac-ac delta rise, fall rate and dc-dc delta rise, input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc), similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example : if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is - 0.5ns/v . using the table given, this would result in the need for an increase in tds and tdh of 100 ps. k. table 3 is used to increase tds and tdh in the case where th e i/o slew rate is below 0.5 v/ns. the i/o slew rate is based on the lesser on the lesser of the ac - ac slew rate and the dc- dc slew rate. the inut slew rate is based on the lesser of the slew rate s deter mined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc), and similarly for rising transitions. l. dqs, dm, and dq input slew rate is sp ecified to prevent double clocking of data and preserve setup and hold times. signal tr ansi tions through the dc region must be monotonic. a. pullup slew rate is characteristized unde r the test conditions as shown in figure 2. output test point v ssq 50 ? figure 2 : pullup slew rate test load 23.0 system notes rev. 1.2 feburary 2009 ddr sdram k4h281638l 27 of 32 figure 4. i/v characteristics for input/output buffers:pulldown(above) and pullup(below) ddr sdram output driver v-i characteristics ddr sdram output driver characteristics are defined for full and half strength operation as se lected by the emrs bit a1. figures 4, 5 and 6 show the driver characteri stics graphically, and tables 8, 9 and 10 show the same data in tabular format sui table for input into simulation tools. the driver characteristcs evaluation conditions are: output driver characteristic curves notes: 1. the full variation in driver current from minimum to maxi mum process, temperature and vo ltage will lie within the outer bou nding lines the of the v-i curve of figures 4, 5 and 6. 2. it is recommended that the "typical" ib is v-i curve lie within the inner bounding li nes of the v-i curves of figures 4, 5 an d 6. 3. the full variation in the ratio of the "typical" ibis pullup to "typical" ibis pulldown current should be unity +/- 10%, for device drain to source voltages from 0.1 to1.0. this specification is a design ob jective only. it is not guaranteed. typical 25c v dd /v ddq = 2.5v, typical process minimum 70c v dd /v ddq = 2.3v, slow-slow process maximum 0c v dd /v ddq = 2.7v, fast-fast process 24.0 ibis : i/v ch aracteristics for input and output buffers maximum typical high minumum vout(v) iout(ma) -220 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.0 1.0 2.0 minimum typical low typical high maximum 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 iout(ma) typical low vout(v) pull-down characteristics for full strength output driver pull-up characteristics for full strength output driver rev. 1.2 feburary 2009 ddr sdram k4h281638l 28 of 32 table 8. full strength driver characteristics pull-down current (ma) pull-up current (ma) voltage (v) typical low typical high minimum maximum typical low typical high minimum maximum 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 - 18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 - 24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 - 29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 - 34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 - 38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 - 41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 - 41.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 - 46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 - 47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 - 49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 - 50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 - 50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 - 50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51 .0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -5 1.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -5 1.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -5 1.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51 .6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 -51 .8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52 .0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52 .2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52 .3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52 .5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52 .7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52 .8 -160.1 -41.2 -198.2 rev. 1.2 feburary 2009 ddr sdram k4h281638l 29 of 32 figure 5. i/v characteristics for input/output buffers:pulldown(above) and pullup(below) maximum typical high minumum vout(v) iout(ma) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 1.0 2.0 iout(ma) minimum typical low typical high maximum 0 10 20 30 40 50 60 70 80 90 0.0 1.0 2.0 iout(ma) typical low vout(v) pull-down characteristics for weak output driver pull-up characteristics for weak output driver rev. 1.2 feburary 2009 ddr sdram k4h281638l 30 of 32 pull-down current (ma) pull-up current (ma) voltage (v) typical low typical high minimum maximum typical low typical high minimum maximum 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 - 13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 - 16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 - 19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 - 21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 - 23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 - 24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 - 26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 - 27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 - 27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 - 28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 - 28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 - 28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 - 28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 - 28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 - 29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 - 29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 - 29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 - 29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 - 29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 - 29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 - 29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 - 29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 - 29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 - 29.9 -65.8 -23.3 -79.7 table 9. weak driver characteristics rev. 1.2 feburary 2009 ddr sdram k4h281638l 31 of 32 figure 6. i/v characteristics for input/output buffers:pulldown(above) and pullup(below) pull-down characteristics for matched output driver pull-up characteristics for matched output driver 0 10 20 30 40 50 60 70 0.0 1.0 2.0 minimum maximum iout(ma) vout(v) maximum minumum vout(v) iout(ma) -70 -60 -50 -40 -30 -20 -10 0 0.0 1.0 2.0 rev. 1.2 feburary 2009 ddr sdram k4h281638l 32 of 32 table 10. matched driver characteristics pull-down current(ma) pull-up current (ma) voltage (v) minimum maximum minimum maximum 0 0.0 0.0 0.0 0.0 0.2 3.6 7.8 -4.4 -8.8 0.4 7.3 15.8 -8.8 -15.7 0.6 11.0 23.1 -13.3 -23.0 0.8 14.6 29.4 -17.3 -29.4 1.0 16.8 35.5 -18.6 -35.4 1.2 18.3 41.0 -18.9 -41.0 1.4 18.8 46.1 -19.0 -46.0 1.6 19.0 50.5 -19.3 -50.3 1.8 19.6 53.8 -19.5 -53.8 2.0 19.7 57.3 -19.6 -57.2 2.2 19.8 60.1 -19.7 -60.1 |
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